The present invention relates generally to memory systems and more particularly to decoder apparatus and methodologies for reading data from memory core cells during a memory read operation.
Flash and other types of electronic memory devices are constructed of thousands or millions of memory cells, adapted to individually store and provide access to data. A typical memory cell stores a single binary piece of information referred to as a bit, which has one of two possible states. The cells are commonly organized into multiple cell units such as bytes which comprise eight cells, and words which may include sixteen or more such cells, usually configured in multiples of eight. Storage of data in such memory device architectures is performed by writing to a particular set of memory cells, sometimes referred to as programming the cells. Retrieval of data from the cells is accomplished in a read operation. In addition to programming and read operations, groups of cells in a memory device may be erased, wherein each cell in the group is programmed to a known state.
The individual cells are organized into individually addressable units or groups such as bytes or words, which are accessed for read, program, or erase operations through address decoding circuitry, whereby such operations may be performed on the cells within a specific byte or word. The individual memory cells are typically comprised of a semiconductor structure adapted for storing a bit of data. For instance, many conventional memory cells include a metal oxide semiconductor (MOS) device, such as a transistor in which a binary piece of information may be retained. The memory device includes appropriate decoding and group selection circuitry to address such bytes or words, as well as circuitry to provide voltages to the cells being operated on in order to achieve the desired operation.
The erase, program, and read operations are commonly performed by application of appropriate voltages to certain terminals of the cell MOS device. In an erase or program operation the voltages are applied so as to cause a charge to be stored in the memory cell. In a read operation, appropriate voltages are applied so as to cause a current to flow in the cell, wherein the amount of such current is indicative of the value of the data stored in the cell. The memory device includes appropriate circuitry to sense the resulting cell current in order to determine the data stored therein, which is then provided to data bus terminals of the device for access to other devices in a system in which the memory device is employed.
A typical single bit type memory cell may be programmed by applying a relatively high voltage to the control gate and a moderately high voltage to the drain, in order to produce xe2x80x9chotxe2x80x9d (high energy) electrons in the channel near the drain. The hot electrons accelerate across the tunnel oxide and into the floating gate, which become trapped in the floating gate because the floating gate is surrounded by insulators. As a result of the trapped electrons, a threshold voltage of the memory cell increases. This change in the threshold voltage (and thereby the channel conductance) of the memory cell created by the trapped electrons is what causes the memory cell to be programmed.
To read the memory cell, a predetermined gate voltage greater than the threshold voltage of an unprogrammed memory cell, but less than the threshold voltage of a programmed memory cell, is applied to the gate. If the memory cell conducts (e.g., a sensed current in the cell exceeds a minimum value), then the memory cell has not been programmed (the memory cell is therefore at a first logic state, e.g., a one xe2x80x9c1xe2x80x9d). If, however, the memory cell does not conduct (e.g., the current through the cell does not exceed a threshold value), then the memory cell has been programmed (the memory cell is therefore at a second logic state, e.g., a zero xe2x80x9c0xe2x80x9d). Thus, each memory cell may be read in order to determine whether it has been programmed (and therefore identify the logic state of the data in the memory cell).
Flash memory is a type of electronic memory media which can be rewritten and hold its content without power. Flash memory devices generally have life spans from 100 K to 10 MEG write cycles. Unlike dynamic random access memory (DRAM) and static random access memory (SRAM) memory chips, in which a single byte can be erased, flash memory is typically erased and written in fixed multi-bit blocks or sectors. Conventional flash memories are constructed in a cell structure wherein a single bit of information is stored in each flash memory cell.
In such single bit memory architectures, each cell typically includes a MOS transistor structure having a source, a drain, and a channel in a substrate or P-well, as well as a stacked gate structure overlying the channel. The stacked gate may further include a thin gate dielectric layer (sometimes referred to as a tunnel oxide) formed on the surface of the P-well. The stacked gate also includes a polysilicon floating gate overlying the tunnel oxide and an interpoly dielectric layer overlying the floating gate. The interpoly dielectric layer is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate overlies the interpoly dielectric layer.
More recently, flash memory devices have incorporated dual bit cell architectures, in which the core cells can each store two data bits. Dual bit memory cells are generally symmetrical, wherein the drain and source terminals are interchangeable. When appropriate voltages are applied to the gate, drain, and source terminals, one of the two bits may be accessed (e.g., for read, program, erase, verify, or other operations). When another set of terminal voltages are applied to the dual bit cell, the other of the two bits may be accessed.
Core cells in flash memory devices, whether single bit or multiple-bit, may be interconnected in a variety of different configurations. For instance, cells may be configured in a NOR configuration, with the control gates of the cells in a row individually connected to a word line. In addition, the drains of the cells in a particular row are connected together by a conductive bit line. In the NOR configuration, each drain within a single column is connected to the same bit line. In addition, each flash cell associated with a given bit line has its gate coupled to a different word line, while all the flash cells in the array have their source terminals coupled to a common source terminal, such as Vss or ground. In operation, individual flash cells in such a NOR configuration are addressed via the respective bit line and word line using peripheral decoder and control circuitry for programming (writing), reading, erasing, or other functions.
Another cell configuration is known as a virtual ground architecture, in which the gates of the core cells in a row are tied to a common wordline. A typical virtual ground architecture comprises rows of flash memory core cell pairs with a drain of one cell transistor coupled to an associated bit line and the source of the adjacent core cell transistor. An individual flash cell is selected via the word line and a pair of bit lines bounding the associated cell. For instance, such a cell may be read by applying voltages to the gate (e.g., via the common wordline) and to a bit line coupled to the drain, while the source is coupled to ground (Vss) via another bit line. A virtual ground is thus formed by selectively switching to ground the bit line associated with the source terminal of only those selected flash cells which are to be read. In this regard, where the core cells are of a dual bit type, the above connections can be used to read a first bit of the cell, whereas the other bit may be similarly read by grounding the bitline connected to the drain, and applying a voltage to the source terminal via the other bitline.
Where a virtual ground type core architecture is employed, problems may arise in reading the individual core cells (e.g., single bit or dual bit) comprising a group, such as a byte, word, etc. For instance, because all the cells associated along a word line have their drains and sources coupled in series, these cells have a combined leakage path through the drain or source side of the cell being sensed. The leakage current related to adjacent cells in the virtual ground type configuration may thus result in false readings of the data actually stored in a given cell, since the cell is read by sensing the current. Hence, there is a need for improved methods and apparatus by which the adverse effects of adjacent cell leakage current can be reduced or mitigated in virtual ground type flash memory devices.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor to delineate the scope of the invention. Rather, the primary purpose of this summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later. The invention provides methods and apparatus by which the above shortcomings associated with reading virtual ground memory cells can be mitigated or overcome. The invention involves precharging one or more cells adjacent to a target cell of interest read, by which leakage current from such an adjacent cell can be reduced or mitigated during a read operation in a virtual ground memory device. Decoder circuitry and methodologies are provided for advantageous connection of the target cell and an adjacent cell to appropriate voltages or ground in order to facilitate the reading and precharging thereof, respectively. The invention thus provides for decoding of address lines associated with a virtual ground type memory device to provide appropriate connection to the core cells of interest through one or more switches in the decoder circuitry.
One aspect of the invention provides a memory device, wherein a memory core comprises a plurality of core memory cells organized in a virtual ground configuration. In such a configuration, adjacent memory cells (e.g., single or dual bit) have their gates tied to a common wordline, and the drain of one cell is tied to the source of an adjacent cell. The nodes connecting source and drain terminals are used as local bitlines to select the desired memory cell for read operations. For example, a memory device according to this aspect of the invention has a plurality of memory cells including a first cell with a drain connected to a first bitline, as well as a source connected to a second bitline. A second cell has a drain connected to the second bitline and a source connected to a third bitline. A third cell in the device has a drain connected to the third bitline and a source connected to a fourth bitline. The device further comprises a decoder which operates to precharge one of the first and third cells during a read operation associated with the second cell. The decoder, for example, may connect a read voltage to the drain of the second cell, and a precharge voltage to one of the adjacent cells while grounding the second cell source terminal. A current associated with the second cell can then be measured without adverse leakage current from the adjacent cells. The invention thus provides for improved cell reading in virtual ground type cell configurations, which can be used in association with single bit or dual bit type cell architectures.
The decoder comprises various switching devices, such as MOS type transistors, which are selectively activated according to the address lines of the memory device in order to read appropriate memory cells. The decoder can include a plurality of global bitlines, a plurality of intermediate bitlines, and a plurality of local bitlines individually connected to a source of one cell and a drain of an adjacent cell. Various switches are positioned between the global, intermediate, and local bitlines, which are used to connect various voltages or ground to the terminals of the target memory cell and an adjacent cell. Byte select switches are employed to connect drain read voltages, ground, and precharge voltages to individual global bitlines, which are selectively connected to intermediate and local bitlines using column select switches and sector select switches, respectively, according to decoder switching signals.
According to another aspect of the invention, methodologies are provided for reading a memory cell of a virtual ground memory core in a memory device. The methods can include selecting a first memory cell in the memory core to be read, precharging one of second and third memory cells adjacent to the first memory cell, and sensing a current associated with a terminal of the first cell to ascertain data associated with the cell. The first memory cell can be selected by connecting one of the drain and source terminals to a read voltage and connecting the other to ground. For instance, a first global bitline is connected to the read voltage, which is then connected to the drain, and a second global bitline is connected to ground, which is then connected to the source. Precharging the adjacent cell can be accomplished by connecting a third global bitline to a precharge voltage and connecting the third global bitline to a local bitline associated with the appropriate adjacent cell.